A key component in improving the speed of modern digital computers is to reduce the propagation delay of the circuits used to perform the necessary logic and communications operations. The speed or propagation delay of a circuit is ultimately limited by the speed of the individual transistors from which it is built. A fundamental limit to the speed of a transistor is given by the time required for the minority carrier distribution in the base region to respond to a change in base current and cause an amplified change in collector current. A measure of this time is given by the minority carrier base transit time EQU T=W.sup.2 /2D
for a linear carrier distribution where
T is the base transit time, PA1 W is the transistor base width, and PA1 D is the carrier diffusivity in the base. PA1 q is the magnitude of the electronic charge, PA1 Q is the base doping, PA1 Ke is the permittivity of the semiconductor, PA1 W is the base width, and PA1 N is the collector doping.
The base width is thus seen to have a direct bearing on the transistor speed and thus affects the speed of machines, such as computers, which are made from them. In order to minimize the propagation delay of a circuit, transistors with the smallest obtainable base width are required.
The logic circuits in a computer do not exist in isolation. They must be able to electrically communicate with circuits and devices made from different materials and with different operating characteristics. Examples of such interfaces would be communications with field effect transistor memory array chips and communications with sections of the machine built from industry standard 5 volt logic circuits.
These other circuits have specific electrical interface specifications in regard to voltage and current levels that must be met with the same type of devices and on the same integrated circuit chip that form the high speed digital logic circuits. A critical parameter for the devices forming the interface circuits is the transistor breakdown voltage. This voltage limits the use of the transistors to those interface applications that will not overstress the device and cause device or circuit failure. A measure of this is given by the transistor collector to emitter punch-through voltage, EQU BV=(qQ/(Ke))(W+Q/(2N))
where
The base width is thus seen to have a direct bearing on the transistor breakdown voltage and thus limits the range of interface applications. In order to maximize the breakdown voltage of the transistor, the largest possible base width is required.
These two desirable transistor characteristics, high speed and high breakdown voltage, are seen to be in conflict. The doping concentrations and base widths that result in high speed devices severely limit the transistor breakdown voltage and thus limit the use of the transistors in interface circuit type applications. In fact, transistors presently designed for state of the art fast switching speeds are incapable of sustaining the voltage levels (three to five volts) required to interface to FET memory array chips and industry standard TTL circuits.
The conventional solution to this problem is to use special interfacing integrated circuits that can receive the levels generated by the high speed logic chips and convert them to the larger standard interface signal levels. These special interfacing integrated circuits are made by a process different from that of the high speed circuits and will support the higher voltage levels, although at a correspondingly lower performance and with greater propagation delay. This approach causes problems in the design of a high performance system not only because the interfacing circuits are manufactured by a lower performance process but because the additional circuits introduce more circuit chips both in the logic path and in the machine, causing physical packaging difficulties and total logic path and transmission line delay increases. This causes the assembled digital system to run slower and cost more than it would if the interface circuits could be integrated at will on the high speed logic chips.
My invention presents a circuit solution to the transistor speed vs. breakdown voltage problem. Transistors, formed by a process that results in maximum speed, are connected in series such that the total applied voltage divides between them. In this manner, no one transistor must support the entire voltage swing and each device is operated within its breakdown voltage rating. However, because of the multiple connection of series transistors, an arbitrarily large voltage swing may be built up, satisfying any interfacing requirement. Furthermore, the disclosed circuits are true digital logic circuits having only two possible output voltage levels near each power supply extreme, resulting in maximum circuit efficiency. The circuit voltage gain in each of the binary states is zero, insuring stable output levels. A most important aspect of operation of the disclosed circuits is that the series transistors maintain the voltage division even during the dynamic switching interval when the circuit output changes between the binary states. Thus the transistors are always protected from overvoltage, even while switching states from "on" to "off".
Specific embodiments of my invention are fully disclosed hereinafter. The key feature of my invention centers around an upper series connected transistor with its emitter and base resistors and base voltage dropping base-collector diode. As fully described hereinafter, these components act to control the voltage seen by the transistor and keep it within its safe operating region during switching. Several similar stages may be combined in series to increase the output swing beyond what is shown.